In recent years, as for liquid crystal display devices, a gate driver (scanning signal line drive circuit) for driving gate bus lines (scanning signal lines) have become increasingly monolithic. Conventionally, a gate driver has mostly been mounted as an IC (Integrated Circuit) chip on a peripheral part of a substrate that constitutes a liquid crystal panel. However, in recent years, it has gradually become more common to provide a gate driver directly on a substrate. Such a gate driver is called such as a “monolithic gate driver”. In a liquid crystal display device provided with a monolithic gate driver, a thin-film transistor using amorphous silicon (a-Si) (hereinafter referred to as an “a-SiTFT”) has been conventionally employed as a drive element. However, a thin-film transistor using microcrystalline silicon (μc-Si) or oxide semiconductor (e.g., IGZO) has become commonly employed in recent years. Mobility of microcrystalline silicon and oxide semiconductor is greater than that of amorphous silicon. Therefore, it is possible to achieve reduction of a picture-frame area and improved resolution by employing a thin-film transistor using microcrystalline silicon or oxide semiconductor as the drive element.
A display unit of an active matrix-type liquid crystal display device includes a plurality of source bus lines (video signal lines), a plurality of gate bus lines, and a plurality of pixel formation portions provided respectively corresponding to intersections between the plurality of source bus lines and the plurality of gate bus lines. These pixel formation portions are arranged in matrix to constitute a pixel array. Each pixel formation portion includes a thin-film transistor as a switching element having a gate terminal connected to a gate bus line that passes through the corresponding intersection and a source terminal connected to a source bus line that passes through this intersection, a pixel capacitance for storing a pixel voltage value, and so on. Such an active matrix-type liquid crystal display device is also provided with the above-described gate driver, and a source driver (video signal line drive circuit) for driving the source bus lines.
Although video signals indicating pixel voltage values are transmitted through the source bus lines, the source bus lines cannot transmit video signals indicating pixel voltage values for more than one line at one time (simultaneously). Therefore, writing (charging) of the video signals to the pixel capacitances in the pixel formation portions arranged in matrix is performed sequentially line by line. Thus, the gate driver is configured by a shift register having a plurality of stages so that the plurality of gate bus lines are sequentially selected for a predetermined period. Each stage of the shift register takes one of two states (a first state and a second state) at each time point, and outputs a signal indicating this state (hereinafter referred to as a “state signal”) as a scanning signal. Then, video signals are written sequentially line by line to the pixel capacitances as described above by active scanning signals being outputted sequentially from the plurality of stages constituting the shift register.
In a conventional display device, each stage of the shift register is configured as illustrated in FIG. 37 (FIG. 2 of Japanese Patent Application Laid-Open No. 2006-127630) or in FIG. 38 (FIG. 2 of U.S. Pat. No. 7,529,333) (FIG. 38 illustrates two stages). Each stage of them is provided with an output control transistor having a source terminal connected to a scanning signal output terminal and a drain terminal supplied with a clock signal. Then, an ON/OFF state of the output control transistor is controlled by controlling a potential of a node connected to a gate terminal of the output control transistor, and a potential of a clock signal when the output control transistor is in the ON state appears as a scanning signal. It should be noted that FIG. 39 is a circuit diagram showing a configuration of two stages in a shift register of the conventional display device, and the two stages correspond to a stage constituent circuit according to a first embodiment that will be later described.
Further, Japanese Patent Application Laid-Open No. 2008-508654, Japanese Patent Application Laid-Open No. 2008-537275, Japanese Patent Application Laid-Open No. 2002-203397, and Japanese Patent Application Laid-Open No. 2008-61323 also disclose a configuration of a shift register provided for a display device and such.